Employment |
| 02-17 00:50:14 来源： 作者： |
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Employment Inquiry (采购产品): Employment Hi, My friend told me about your company might be looking for some hardware engineers. Please take a look at my resume and give me a call if you have a position with my skill set. Thank you. KHIEM V. NGUYEN Cell: 858-205-8413 Address: 3221Mt.Whitney Rd. Home: 760-743-5987 Escondido, Ca. 92029 Email: khiem2000@hotmail.com PROFESSIONAL SUMMARY: ? Broad strong technical knowledge and hands-on experience in design/validation of FPGAs, CPLDs by using VHDL and Verilog language and Circuit Boards design from specification to end product; Hardware Designer in the telecommunication R&D environment, specialize in wireless electronic communication systems. ? Experienced designing in the following areas: Avionics, Transceivers, RF and PA Controls, GSM Base Station Transceiver, Ethernet, PCI, CDMA, Modem, Video, Audio. EXPERIENCE: General Atomics 08/2008 – Present Consultant ? Responsible Design Engineer ASIC/ FPGA. Design and Verification and Implementation radar control systems, Design exposure control for high speed camera, Update existing master state machine to control radar, image processing, clocks and power control. ? Integration and Test image processing and radar control with Xilinx Virtex4. ? Module and Top level VHDL verification with Cygwin and Modelsim environment. Sandel Avionics 11/2006 - 06/2008 Sr. Staff Engineer ? Responsible Design Engineer for all FPGA Designs for the SA4550 Primary Attitude Display. The task included writing Complex Logic Requirements. Xilinx Spartan 3S and 3E FPGA Partitioning, Design and Implementation of graphic controller to interface to Seiko-Epson LCD ICs, GPCM interface, DMA controller to interface to Freescale Power PC 8250, ARINC-429, RS-422, Interlink serial interface, PWM encoder, Backlight control, DAC, ADC, I2C, SPI, FLASH controller. Verilog RTL coding and gate simulation, synthesis and place and route. Support I&T functions. Prepare all documentations related to DO-254 and interface to FAA DER for FAA D0-254 Level A,B and C Certification. ? Responsible Design Engineer for board design, FPGA design for the SN4500 Primary Navigational Display with video capability, Schematic, design, board layout, RTL coding and simulation. Implement design using Xilinx Virtex 2 FPGA and Spartan 3. Support I&T. ? Module and Top level Verilog verification with TCL scripts and Modelsim environment. Northrop Grumman (RS) 04/2001 - 11/2006 Sr. Staff Engineer ? Responsible Design Engineer for L-Band Power Amplifier FPGA Design. The task included writing VHDL Requirements Specifications. Xilinx V4FX FPGA Partitioning, Design and Implementation of SoC consisting of PowerPC 405, Tri-Mode Ethernet MAC. Implement Ethernet Interface, Message Router, Logic Control, Synthesizer, AGC, DAC, ADC, I2C, SPI, FLASH, SDRAM controller. RTL coding and gate simulation, synthesis and place and route. Support I&T functions. ? Develop Radio Frequency Control Module. Logic Design, RTL coding and simulation. Implement design using Xilinx Virtex 4 FPGA. Support I&T. ? Develop proprietary Communication Interface Module for DSP to communicate with waveforms. ? FPGA Design and Implementation of Dual Transceivers for commercial base station, Using 2 Xilinx Virtex 2 FPGA. The work included designs and implementation of pulse modulation, pre-distortion, microprocessor core to support diagnostic functions necessary to integrate with the GSM base station subsystems. Xilinx FPGA, RTL and gate simulation, synthesis and place and route. The specific tasks include clock generation and power management module, clock tree definitions, top-level static timing analysis. ? Perform module simulation and verification with Modelsim. Motorola (PCS) 08/1999 - 04/2001 Staff Engineer ? Develop third generation wireless phone using Qualcomm CDMA 1X chipset. Designing with MSM5100 Baseband to interface with companion IF and RF devices. Implement Bluetooth solution using Broadcom RF FE IC according to BlueQ specification. ? Develop high performance wireless phone using Motorola CDMA chipset. Schematic design of baseband portion. Design glue logic using Altera EPLD to implement Motorola Smart module bus (P2K platform). ? Perform simulation with Altera Quartus Tool. ? Develop Bluetooth module to interface with Motorola CDMA phone through Smart module bus. Using DigiAnswer Baseband and National Semiconductor RF chipset. ? Develop Bluetooth testing procedures for cell phone to ensure compliance with Bluetooth specifications and Bluetooth SIG profiles such as SDA, headset, dial-up, LAN access profiles. ? Develop and test Bluetooth antenna solution for cell phone and PDA applications. ? Integrating GPS, Bluetooth and E-Commerce modules to performance category phone. ? Designing Brassboard to test and troubleshoot next generation wireless phone. ? Schematics capture using Mentor Graphic Designer and PCB layout. Sony-PMCA / WTDA (Wireless group) 02/1997 - 08/1999 Sr. Engineer ? Designed smart phone (TNL) base on Qualcomm MSM chipset interfacing with NEC RISC Vr4002 processor and SONY ASIC to perform video, audio and WEB enable functions. ? Designed hardware and firmware for wireless local loop module to interface with Sony handset Z100 for hand-free application. ? Designed and developed baseband section for 3G-CDMA2000 mobile station. ? Used multiple Xilinx FPGAs and TI C54 DSP and ARM7TDMI for speech Encoder/Decoder, equalizer/AGC processing and control functions. Baseband board also interfaced with two Pentek DSP Boards through VME bus for modem functions and Rake Receivers etc. ? Designed and debugged PLL daughter board to provide system clock 29.4912 MHz. ? Designed and developed FPGAs downloading schemes using 80C51 microcontroller; interface with PC to download configuration data to FPGAs using HDLC protocol. ? Designed Data Generation circuit for cdma2000 Mobile Station. ? EPLD programming using VHDL for implementing Multiplexing and glue logic. ? Schematics capture using Cadence Concept and Alegro for PCB layout. Business Managing and Network Consultant , 07/1989 - 11/1996 ? Developed low cost modem for PC companies using Rockwell chipset. Installed and managed Novell NetWare 2, 3 and 4 servers for small companies and retail businesses with multiple workstations and two servers using Star Bus topology and Ethernet NIC. ? Experienced in Windows NT server 4.0 and Client/Server environment. Helped to build an Intranet and developed web site for Escondido School District in San Diego. ? Owning and managing several businesses in San Diego. Computer Consoles Inc. 06/1987 - 07/1989 Digital Engineer ? Developed a 68010-based multi-protocol communication controller (X.25, ASYNC,SDLC,HDLC) using C language and Assembly to develop X.25 protocol. Computer Consoles Incorporate. Irvine, CA. Rockwell International 07/1980 - 06/1987 Engineer ? Developed hardware and firmware for Rockwell custom stand alone box modem using Rockwell chipset and development tools. ? Developed internal and external private label modems with extensive customer interfacing and specification development. ? Implemented Microcom Networking Protocol (MNP) level 1,2,3 using R6500/12. ? Implemented Hayes Auto dialer and synchronous auto dialer for Bysync and SDLC protocol. ? Developed firmware to implement private command sets for private modems. ? Developed application software on PC to test modem performance (BER) and functionality. ? Developed transmitter and receiver analog filters for medium speed modems. EDUCATION: ? M.S, Electrical Engineering (January 1984) West Coast University ? B.S., Electrical Engineering (June 1981) University of California, Irvine ? Certified Novell Engineer (September 1996) INACOM Education Center. San Diego. ? Certified Microsoft Networking Specialist INACOM Education Center. San Diego. ? CDMA Engineering Certification UCSD 2002. ? Completed CDMA and CDMA 2000 Training at SONY. ? Completed TDMA Training at Motorola University. ? Completed Cadence Training at Sony. ? Completed HP Advance Design System, RF and Microwave at Motorola. ? Completed Mentor Graphic training at Mentor Graphic. ? Completed Altera Training on VHDL |
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