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| 03-22 16:45:10 来源： 作者： |
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Resume Inquiry (采购产品): Resume Resume of Marc de la Chevrotiere 13759 60th Street North Clearwater, Florida 33760 22711 Oakcrest Circle, Yorba Linda, CA 92887 Phone: (727) 543-0553 Phone: (909) 548-9478 E-mail:MC@ProactiveDesignSolutions.com Looking for Contract Work - I Have Licensed Copies of Software Listed Below PADS Layout 2005 SP2; PADS Logic 2005 SP2; PADS Router 2005; Orcad Capture (V10.5); Orcad Layout (V10.5); DxDesigner(V2005); PCAD 2004 Schematic SP4; PCAD 2004 Layout SP4; AutoCad LT 2005; Cam 350 V9.1; Gerbtool V13.0.1; Windows XP Professional. Technical Training: Received diploma for a two year electronics technician program. Accel EDA PCAD and Tango user training and HP3075 functional test development user training. Jan 98 to Present Proactive Design Solutions (Part-Time Design Consultant) (Independent Design Consultant) Working on-site/off-site for PCB Layout and Schematic Capture. Setting up libraries, default cam files, default design rules, generating in-house DFM document for design, test and manufacture. Working with manufacturing personnel to improve libraries minimizing part movement, tombstoning, thermal fatigue thereby improving solder fatigue resistance. Improve CTE loading between component and board substrate by tailoring copper balance to minimize plastic deformation on solder joints. Working knowledge of different soldering alloys and their impact on fatigue resistance, thermal fatigue, melting temperature, intermetallic compounds, tensile strength, etc…. Involved in making the transition to lead-free. High-density double-sided SMT for analog, high-speed digital, RF and microwave applications. Controlled impedance utilizing coplanar wave guide, stripline, dual stripline and microstrip for 50-ohm transmission. 1mm and 0.8mm BGAs using .005.005 line width/spacing. Understanding of TEM, quasi-TEM and TE/TM transmission modes. Understanding of clock distribution techniques. Understanding of wave propagation and different termination techniques, reflection coefficients, impedance discontinuities, RF return paths, clock and critical net distributions, flux cancellation, via capacitance and inductance, match lengths, differential pairs, etc… Familiar with HALT, HASS and HASA accelerated reliability test methods. EMC/EMI Six Sigma regular practitioner. Work alongside engineering and manufacturing assisting in developing a packaging strategy (i.e. layer count and stackup arrangement, surface finish, glass style selection, trace width, copper weight, etc...) and assist in component selection to address moisture absorption, lead surface roughness, die cracking, part cracking and component popcorning by paying attention to JEDEC moisture sensitivity levels. Create rules-driven A-D startup files for DFSS (Design for Six Sigma) effort. Footprint and symbol creation with reference to JEDEC publication 95 and IPC-SM-782. Pay meticulous attention to land patterns and understand how they influence solder fatigue and crack propagation. Research existing and next generation second-level packaging solutions on high I/O devices from a density and reliability standpoint. Understand different component packaging solutions of organic and inorganic BGA ( overmold, glob-top, TBGA, C4 and ceramic ). Understand the use of anisotropic (ACA) and isotropic (ICA) conductive adhesives and epoxy underfills as they relate to Flip-Chip and Direct Chip Attach (DCA) assemblies. Understand electrical, mechanical and thermal fatigue failure mechanisms. Be aware of thermal expansion stress concentrations between component substrate to board substrate and component-substrate to die-substrate on BGA and DCA packages that use low and high-melt flip-chip connections. Researching different methods and materials for microvia formation including photodefined vias, laser(CO2, UV-YAG and Excimer and plasma) using resin-coated copper(RCC), photoimageable and conventional dielectrics. Familiar with Buried-Bump Interconnection Technology(B2IT) and Any Layer Inner Via Hole(ALIVH). Familiar with parallel and sequential lamination (SBU – sequentially built up). Working knowledge of PTFE/Woven Glass, PTFE/Ceramic, Polyimide, Cyanate Ester/Woven Glass, Non-Woven Thermount, standard FR-4 and new lead-free laminates. Analyzing different Finite Element Modeling (FEM) software packages to implement at the PCB and library level to minimize CTE loading between solder, component and board substrate thereby increasing solder fatigue life. Familiar with Flip Chip, BGA, DCA and Stacked CSP. Prepreg, glass styles, warp and fill, different resin systems. DMA and TMA. June 2004 to April 15, 2006 GE Transportation (contract) Schematic capture and printed circuit board layout for the railroad industry using PADS Layout and PADS Logic. Design of hi-speed (100MHz) digital up to 16-layer designs utilizing 50 ohm microstrip and dual stripline techniques. Double-sided, high-density EMC compliant designs. Fine-line routing. 1mm and 0.8mm BGAs. Split planes for power and ground providing short return paths and lower power to ground impedance. Double-sided surface-mount (Type I, II and III assemblies) using convection reflow and wave solder. Process gerber files, get board quotes and issue drawing packages to vendors(gerber files, stencil files, etc…), panelize boards for production, implement ECOs, generate assembly drawings, maintain libraries and generate internal printed circuit board layout design standards. Involved in lead-free transition. Work closely with engineering through initial design review, component selection and analysis of second-level packaging probability. Review testability strategy/coverage and propose a tentative interconnect methodology that effectively addresses, minimizes and manages all design constraints and variables. Assign MLB stackup defining conductor type (ED or RA), dielectric type and thickness, prepreg type and thickness, define via usage/type as well as selecting surface finish (Immersion Tin, Electroless Nickel/Immersion Gold, Entek, HASL). Consider functional-based requirements (dissipation factor, dielectric constant, surface roughness ...) and material-based requirements (black pad, tin whisker, dimensional stability, thermal stability, flexural strength, moisture absorption, Tg, peel strength, CTE, CHE ...) Work with vendors on via plugging/tenting for boards to be in-circuit tested (ICT). Work with development team to determine test strategy, i.e., in-circuit test and/or boundary scan techniques, break out test fixture, etc… Handle everyday questions/problems from PCB vendors, engineering and manufacturing. Make suggestions for improvement to reduce design cycle time and minimize design passes. Researching different design interconnect techniques for High Density Interconnections (HDI). Implement final design validation. Oct 2003 to Dec 2003 Northrop Grumman (Xetron Division) (contract) Schematic capture and printed circuit design designing radios and switching power supplies for the military. Initiating design reviews, assisting in component selection, testability and providing packaging solutions. Implementing engineering change orders. Multilayer designs up to 10 layer designs for EMC compliance utilizing stripline, microstrip, 3W, 10W and 20H design rules and techniques. Aug 2003 to Oct 2003 Harris Corporation (RF Communications Division) (contract) Schematic capture and printed circuit design designing radios for the military. Initiating design reviews, implementing engineering change orders designs up to 10 layer designs (rigid and sculptured flex) for EMC compliance utilizing stripline, microstrip, 3W, 10W, 20H design rules and techniques. Sep 2002 to Jan 2003 Philips Semiconductor (contract) PCB design using Power PCB V5.0 and BlazeRouter to support R&D for new product validation and verification for high definition television (HDTV). Using Orcad Capture (V9.2.2) to implement schematic changes, generate netlists, run DRC, etc... Designs include hi-speed digital (133MHz) external bus speed, controlled-impedance (50-ohm), double-sided SMT multilayers utilizing TEM stripline and Quasi-TEM microstrip techniques. |
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